This invention relates to data clocking and detection for digital data storage systems such as tape drives and more particularly, to an improved digital data clocking and detection system.
When stored digital data is played back from a data storage system, such as a magnetic tape or disk system, it is necessary to determine both the frequency and the phase of the transitions in the played back signals. In magnetic tape storage the data is typically stored in nine tracks which contain transitions representing ones and zeroes making up digital data words. A separate clock track is not normally recorded. From the played back data itself, the proper clocking must be determined in order to define the limits of the bit cells in each track.
Since the speed of the magnetic medium upon which the data is recorded may vary slightly, the frequency of the clock pulses defining the edges of the bit cells which are read from the medium must be varied to match these changes in speed. It is common practice to provide a voltage controlled oscillator (V.C.O.) which tracks the detected transitions in order to provide clock pulses having a frequency which varies as the velocity of the magnetic medium changes. Providing proper clocking by itself is not sufficient; the phase of the detected transitions with respect to the clock pulses must also be detected. The two types of commonly used magnetic tape recording systems are ANSI Standard phase encoded (PE) and ANSI Standard GCR recording. In PE recording there is always a transition in the middle of a bit cell and sometimes there is a transition at the edge of a bit cell. In GCR recording, if a bit cell has a transition it is in the middle, not at the edge of the bit cell. Not all GCR bit cells have transitions. In order to properly determine whether the recorded bit is a one or zero, it is necessary for the data detection circuitry to have phase information which defines whether or not a transition occurs in a given bit cell.
Most prior art PE and GCR tape subsystems have used analog phase locked loops and analog data detection circuits for each track. U.S. Pat. No. 4,109,236-Besenfelder shows a digital circuit for clocking and detection. IBM Technical Disclosure Bulletin entitled "DIGITAL PHASE ERROR DETECTOR" by L. Taber, Vol. 23, No. 11, April, 1981 shows a digital phase detector.
In the prior art a phase locked loop and associated circuitry are provided for each data track. This is expensive because it requires a controlled oscillator for each track. There is another problem associated with this approach which is particularly prevalent in high density recording such as is currently practiced with GCR. In such recording a string of bit cells frequently occurs with no transitions. Because of the high density, and the nature of the medium, the transitions at the edge of this string are often shifted so that the transitions appear as a phase error. This incorrectly shifts the frequency of the controlled oscillator in an attempt to compensate for the apparent phase error in this track.
It is an object of the present invention to provide a digital data clocking and detection system in which a common controlled oscillator is used to provide the clock pulses for all tracks thereby effecting a cost reduction.
It is also an object of this invention to provide a digital data clocking detection system which reduces the sensitivity to the high density packing problem described above.
It is also an object of the present invention to provide digital data and phase detection circuitry which replaces the analog circuitry normally associated with these functions.
It is an object of the present invention to compensate for large errors in phase by changing the count in the phase counter associated with the track, whereas smaller phase errors are compensated by controlling the frequency of the controlled oscillator. In this manner, phase deviations, such as caused by skew, are compensated for in each individual track.
It is an object of the present invention to provide data and phase detecting circuitry in which dropout recovery is enhanced.